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rev: 1.00e 6/2002 1/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 18mb 1x2lp double data rate sigmaram? sram 250 mhz?333 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 209-bump bga commercial temp industrial temp features ? double data rate read and write mode ? jedec-standard sigmaram ? pinout and package ? 1.8 v +150/?100 mv core power supply ? 1.5 v or 1.8 v i/o supply ? pipelined read operation ? fully coherent read and write pipelines ? echo clock outputs track data output drivers ? zq mode pin for user-selectable output drive strength ? 2 user-programmable chip en able inputs for easy depth expansion ? ieee 1149.1 jtag-compatible boundary scan ? 209-bump, 14 mm x 22 mm, 1 mm bump pitch bga package ? pin-compatible with future 36mb, 72mb, and 144mb devices sigmaram family overview gs8170dd18/36 sigmarams are built in compliance with the sigmaram pinout standard for synchronous srams. they are 18,874,368-bit (18mb) sr ams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. gsi's rams are offered in a number of configurations that emulate other synchronous srams, such as burst rams, nbt, late write, or double data rate (ddr) srams. the logical differences between th e protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering and write cueing. the ram ? family standard allows a user to implement the interface protocol best suited to the task at hand. functional description because sigmarams are synchronous devices, address and read/write control inputs are cap tured on the rising edge of the input clock. write cycles are inte rnally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. in ddr mode the device captures data in on both rising and falling edges of clock and drives data on both clock edges as well. because the ddr ram always transfers data in two halves, a0 is internally set to 0 for the first half of each read or write transfer, and automatically incremented to 1 for the falling edge transfer. the address field of a ddr ram is always one address pin less than the advertised index depth (e.g., the 1m x 18 has a 512k addressable index). in pipeline mode, single data rate (sdr) rams incorporate a rising-edge-triggered output register. in ddr mode, rising- and falling-edge-triggered output registers are employed. for read cycles, a ddr sram?s output data is staged at the input of an edge-triggered output register duri ng the access cycle and then released to the output dr ivers at the next rising and subsequent falling edge of clock. gs817x18/36/72b rams are implemented with gsi's high performance cmos technology and are packaged in a 209- bump bga. - 333 pipeline mode tkhkh 3.0 ns tkhqv 1.6 ns 209-bump, 14 mm x 22 mm bga 1 mm bump pitch, 11 x 19 bump array bottom view
rev: 1.00e 6/2002 2/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 8170dd36 512k x 36 pinout 512k x 36 common i/o?top view 1234567891011 a nc nc a e2 a adv a e3 a dqb dqb b nc nc mcl nc a w a mcl nc dqb dqb c nc nc nc mcl nc (144m) e1 nc nc mcl dqb dqb d nc nc v ss nc nc mcl nc nc v ss dqb dqb e nc dqc v ddq v ddi v dd v dd v dd v ddi v ddq nc dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd mcl v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss mch v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd nc v ddq v ddi v dd v dd v dd v ddi v ddq dqa nc t dqd dqd v ss nc nc mcl nc nc v ss nc nc u dqd dqd nc a nc (72m) a nc (36m) a nc nc nc vdqddqd aaaa1aaa nc nc wdqddqdtmstdi a mcl a tdo tck nc nc ? 2001.03 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.00e 6/2002 3/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 8170dd18 1m x 18 pinout 1m x 18 common i/o?top view 1234567891011 a nc nc a e2 a adv a e3 a nc nc b nc nc mcl nc a w a nc nc nc nc c nc nc nc nc nc (144m) e1 a nc mcl nc nc d nc nc v ss nc nc mcl nc nc v ss nc nc e nc dqb v ddq v ddi v dd v dd v dd v ddi v ddq nc nc f dqb dqb v ss v ss v ss zq v ss v ss v ss nc nc g dqb dqb v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqb dqb v ss v ss v ss ep3 v ss v ss v ss nc nc j dqb dqb v ddq v ddq v dd mch v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd mcl v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss mch v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r nc nc v ddq v ddi v dd v dd v dd v ddi v ddq dqa nc t nc nc v ss nc nc mcl nc nc v ss nc nc u nc nc nc a nc (72m) a nc (36m) a nc nc nc vncnc aaaa1aaa nc nc wncnctmstdi a mcl a tdo tck nc nc ? 2001.03 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.00e 6/2002 4/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 pin description table pin location symbol description type comments a3, a5, a7, a9, b7, u4, u6, u8, v3, v4, v5, v6, v7, v8, v9, w5, w7 a address input ? c7 a address input x18 version only b5 a address input x18 and x36 versions a6 adv advance input active high k3 ck clock input active high k1, k11 cq echo clock output active high k2, k10 cq echo clock output active low e2, f1, f2, g1, g2, h1, h2, j1, j2, l10, l11, m10, m11, n10, n11, p10, p11, r10 dq data i/o input/output x18 and x36 versions a10, a11, b10, b11, c10, c11, d10, d11, e11, r1, t1, t2, u1, u2, v1, v2, w1, w2 dq data i/o input/output x36 version c6 e1 chip enable input active low a4, a8 e2 & e3 chip enable input programmable active high or low g6, h6 ep2 & ep3 chip enable program pin input ? w9 tck test clock input active high w4 tdi test data in input ? w8 tdo test data out output ? w3 tms test mode select input ? j6, m6, n6 mch must connect high input active high (all versions) b3, c9, d6, k6, l6, p6, t6, w6 mcl must connect low input active low (all versions) b8, c4 mcl must connect low input active low (x36 version)
rev: 1.00e 6/2002 5/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 a1, a2, b1, b2, b4, b9, c1, c2, c3, c5, c8, d1, d2, d4, d5, d7, d8,e1, e10, f10, f11, g10, g11, h10, h11, j10, j11, k4, k8, k9, l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t4, t5, t7, t8, t10, t11, u3, u5, u7, u9, u10, u11, v10, v11, w10, w11 nc no connect ? not connected to die (all versions) c7 nc no connect ? not connected to die (x36 version) a1, a2, b1, b2, b4, b9, c1, c2, c3, c8, d1, d2, e1, e10, f10, f11, g10, g11, h10, h11, j10, j11, l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t10, t11, u10, u11, v10, v11, w10, w11 nc no connect ? not connected to die (x36/x18 versions) a10, a11, b8, b10, b11, c4, c10, c11, d10, d11, e11, r1, t1, t2, u1, u2, v1, v2, w1, w2 nc no connect ? not connected to die (x18 version) b6 w write input active low e5, e6, e7, g5, g7, j5, j7, l5, l7, n5, n7, r5, r6, r7 v dd core power supply input 1.8 v nominal e3, e4, e8, e9, j3, j4, j8, j9, l3, l4, l8, l9, n3, n4, n8, n9, r3, r4, r8, r9 v ddq output driver power supply input 1.8 v or 1.5 v nominal e4, e8, r4, r8 v ddi input buffer power supply input 1.8 v or 1.5 v nominal d3, d9, f3, f4, f5, f7, f8, f9, h3, h4, h5, h7, h8, h9, k5, k7, m3, m4, m5, m7, m8, m9, p3, p4, p5, p7, p8, p9, t3, t9 v ss ground input ? f6 zq output impedance control input low = low impedance [high drive] high = high impedance [low drive] pin description table pin location symbol description type comments
rev: 1.00e 6/2002 6/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 background the central characteristics of rams are that they are extremely fast and cons ume very little power. because both operating and interface power is low, rams can be implemented in a wide (x36) configuration, providing very high single package bandwidth (in excess of 20 gb/s in ordinary pipelined configuration) and very low random access la tency (5 ns). the use of very low volta ge circuits in the core and 1.8 v or 1.5 v interface voltages allow the speed , power and density performance of rams. the ram family of pinouts has been designed to support a number of different common read and write protocols. the following timing diagrams provide a quick comparison between the late write read and write protocol and the ddr protocol options availabl e in the context of the ram standard. this particular datasheet covers the double data rate (ddr) ram. the character of the applications fo r fast synchronous srams in networking systems are extremely diverse. rams have been developed to address the broad variety of applications in the ne tworking market in a manner that can be supported with a unifie d development and manufacturing infrastructure. rams address each of the bus protocol options commonl y found in networking systems. this allows the ram to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older srams, like the nbt, late write, or double data rate srams, as we ll as with new chip sets and asic?s that employ the echo clocks and realize the full potential of the rams. all address and control inputs (with the exception of pe2, pe3, zq, and the mode pins, l6, m6, and j6) are synchronized to ris ing clock edges. data in is captured on both rising and falling edge s of ck. read and write operations must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished by asserti ng all three of the chip enable inputs (e1 , e2, and e3). deassertion of any one of the enable inputs will deactivate the device. it should be noted that only deactivation of the ram via e2 and/or e3 deactivates the echo clocks, cq1?cq2. mode selection truth table standard l6 m6 j6 name function analogous to... in this data sheet? 000 1x1ef early write, flow through read flow through burst ram no 001 1x1lf late write, flow through read flow through nbt sram no 010 rfu n/a 011 1x2lp ddr double data rate sram yes 100 1x1ep early write, pipelined read pipelined burst ram no 101 1x1dp double late write, pipeli ned read pipelined nbt sram no 110 1x1lp late write, pipelined read pipelined late write sram no
rev: 1.00e 6/2002 7/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 read operations double data rate read in applications where a data rate markedly faster than the ra m?s latency is desired, double data rate reads double the data transfer rate (read or write bandwidth) achieved in pipeline mo de while keeping the ram?s clock frequency constant. in double data rate mode, the ram multiplexes the results of a read out of the ram on half the usual number of data pins. the output register/mux behaves just as if it were in pipeline mode for the first transfer, but then makes a second transfer in response t o the next falling edge of clock as well. sigm aram ddr rams burst in linear order only. double data rate pipelined read qa0 qa1 qc0 qc1 qd0 qd1 ck read deselect axx f read read read adv de c /e 1 /w dq address cq key hi-z access
rev: 1.00e 6/2002 8/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 write operations write operation occurs when the following conditions are satisfied at th e rising edge of clock: all three chip enables (e1 , e2, and e3) are active, the write enable input signal (w ) is asserted low, and adv is asserted low. double data rate write a double data rate write is a specialized form of late write. in double data rate mode, the ram will capture data in on both rising and falling edges of the ram clock, ck, beginning with the rising edge of clock that follows the capture of the write ad dress and command. sigmaram double data rate read and write qa0 qa1 dc0 dc1 qd0 qd1 adv read cq e deselect cd write read read ck address a key hi-z access /e 1 /w dq f b
rev: 1.00e 6/2002 9/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 special functions burst cycles rams provide an on-chip burst address genera tor that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the sram to adva nce the internal address counter and use the counter generated address to read or wr ite the sram. the starting ad dress for the first cycle in a burst cycle series is lo aded into the sram by driving the adv pin low, into load mode. sigmaram ddr burst read with counter wrap-around counter wraps qa2 qa3 qa0 qa1 qa2 qa3 qb0 qb1 adv b3 a2 b0 cq dq /e 1 /w xx internal address a2 a0 b2 b1 a3 continue a1 a3 b1 b0 ck xx read continue external address a2 xx xx continue read
rev: 1.00e 6/2002 10/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 burst order the burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) h ave been accessed. sigmarams always count in linear burst order. linear burst order notes: 1. the burst counter wraps to initial state on the 3rd rising edge of clock. 2. the ddr sigmaram always begins an read or write at a0 = 0. a0 is internally set to 0 at the rising edge of clock and is not available to the user. a[1:0] a[1:0] 1st address (rising edge ck) 00 10 2nd address (falling edge ck) 01 11 3rd address (rising edge ck) 10 00 4th address (falling edge ck) 11 01 sigmaram ddr burst write with counter wrap-around adv db2 cq da2 da3 da0 da1 da2 da3 db0 db1 /e 1 /w dq b2 b3 b1 counter wraps xx internal address a2 a3 a0 a1 a2 a3 b0 b1 xx b0 xx write continue continue write continue ck external address a2 xx
rev: 1.00e 6/2002 11/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 echo clock rams feature echo clocks, cq1,cq2, cq 1, and cq2 that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, ck. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with th e rest of the data output drivers. sigmarams provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs (cq1 and cq2 ). it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. programmable enables rams feature two user-programmable chip en able inputs, e2 and e3. th e sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the prog ramming inputs, pe2 and pe3. for example, if pe2 is held at v dd , e2 functions as an active high enable. if pe2 is held to v ss , e2 functions as an active low chip enable input. programmability of e2 and e3 allows four banks of de pth expansion to be accomp lished with no additional logic. by programming the enable inpu ts of four rams in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four rams can be made to look like one larger ram to the system. example four bank dept h expansion schematic? 1x2lp a ck e1 e2 e3 w a 1 ?a n ck w dq 0 ?dq n bank 0 bank 1 bank 2 bank 3 bank enable truth table ep2 ep3 e2 e3 bank 0 v ss v ss active low active low bank 1 v ss v dd active low active high bank 2 v dd v ss active high active low bank 3 v dd v dd active high active high e1 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 dq a ck e2 e3 w dq a ck e2 e3 w dq a ck e2 e3 w dq e1 e1 e1 cq cq cq cq cq ep2 ep3 0 0 ep2 ep3 1 0 ep2 ep3 0 1 ep2 ep3 1 1
rev: 1.00e 6/2002 12/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. in some applications it may be appropriate to pause between banks; to deselect both rams with e1 before resuming read operations. an e1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the ram in bank 2 to issue at least one cl ock before it is needed. echo clock control in two banks of sigmaram double data rate rams qa0 qa1 qc0 qc1 qb0 qb1 qd0 qd1 note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled f alse. cq1 + cq2 read read dq bank 2 cq bank 2 cq bank 1 read dq bank 1 address a b adv read read f /e2 bank 1 e2 bank 2 cde ck
rev: 1.00e 6/2002 13/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 flxdrive? output driv er impedance control the zq pin allows selection between ram nominal drive strength (zq floating or low) for multi-drop bus applications and low drive strength (zq high) point-to-point applications. s ee ?output driver characteris tics? on page 42 for details. sigmaram ddr bank switch with e1 deselect qa0 qa1 qc0 qc1 qd0 qd1 note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled f alse. f /e2 bank 1 e2 bank 2 dq bank 1 /e 1 c adv read d read dq bank 2 cq bank 1 cq1 + cq2 read cq bank 2 ck e read no op address a xx
rev: 1.00e 6/2002 14/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 late write, pipelined read truth table ck e1 (t n ) e (t n ) adv (t n ) w (t n ) previous operation current operation dq/cq (t n ) dq/cq (t n+? ) dq/cq (t n+1 ) dq/cq (t n+1? ) 0 1 x f 0 x x bank deselect *** hi-z 0 1 x x 1 x bank deselect bank deselect (continue) hi-z hi-z 0 1 1 t 0 x x deselect *** hi-z/cq 0 1 x x 1 x deselect deselect (continue) hi-z/cq hi-z/cq 0 10 t 0 0 x write loads new address *** d1/cq d2/cq 0 1x x 1 x write write continue increments address by 2 dn-2/cq dn-1/cq dn/cq dn+1/cq 0 10 t 0 1 x read loads new address *** q1/cq q2/cq 0 1 x x 1 x read read continue increments address by 2 qn-2/cq qn-2/cq qn/cq qn+1/cq notes: 1. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. 2. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 3. ?***? indicates that the dq input requirement / output state and cq output state are determined by the previous operation. 4. dqs are tri-stated in response to bank deselect, chip deselect, and write comma nds, one full cycle after the command is sampled. 5. cqs are tri-stated in response to ba nk deselect commands only, one full cycle after the command is sampled. 6. one (1) continue operation may be initiated after a read or wr ite operation is initiated to burst transfer a total of four (4 ) dis- tinct pieces of data per single external address input. if a second (2nd) continue op eration is initiated, the internal address wraps back to the initial external (base) address.
rev: 1.00e 6/2002 15/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 common i/o state diagram notes: 1. the notation ?x,x,x,x? controlling the state transitions above indicate the states of inputs e1 , e, adv, and w respectively. 2. if (e2 = ep2 and e3 = ep3) then e = ?t? else e = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. deselect bank deselect read read write write continue x,f,0,x or x,x,1,x continue x,f,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x or x,x,1,x 0,t,0,0 0,t,0,1 0,t,0,0 0,t,0,1 x,f,0,x x,f,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,0 0,t,0,1 1,t,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,1 0,t,0,0 clock (ck) command current state next state ???? current state & next st ate definition for read /write control state diagram current state (n) next state (n + 1) transition ? input command code key nn+1n+2n+3
rev: 1.00e 6/2002 16/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 note: permanent damage to the device may occur if the absolute maxi mum ratings are exceeded. operation should be restricted to recommended operating conditions. exposure to conditions e xceeding the recommended operating conditions, for an extended period of time, may affect reliability of this component. recommended oper ating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddi voltage in v ddi pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to v dd v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v v in voltage on other input pins ?0.5 to v ddi +0.5 ( 2.5 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.8 v input supply voltage v ddi 1.7 1.8 v dd v1 1.8 v i/o supply voltage v ddq 1.7 1.8 v dd v1 1.5 v input supply voltage v ddi 1.4 1.5 1.6 v v 1 1.5 v i/o supply voltage v ddq 1.4 1.5 1.6 v v 1 ambient temperature (commercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ?40 25 85 c2 notes: 1. unless otherwise noted, all perfo rmance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. most speed grades and configurations of this device are of fered in both commercial and industrial temperature ranges. the par t number of industrial temperature range versions end the character ?i?. unless otherwise noted, all per formance specifications quoted a re evalu- ated for worst case in the temperature range marked on the device.
rev: 1.00e 6/2002 17/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 note: this parameter is sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resist ance, mounting board temperature, ambient . temperature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 cmos i/o dc input characteristics parameter symbol min. typ. max. unit notes cmos input high voltage v ih 0.65 * v ddi ? v ddi + 0.3 v1 cmos i/o input high voltage v ih 0.65 * v ddi ? v ddi + 0.3 v1 cmos input low voltage v il ?0.3 ? 0.35 * v ddi v1 note: for devices supplied with cmos input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. capacitance (t a = 25 o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf output capacitance c out v out = 0 v 67pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r ja tbd c/w 1,2 junction to ambient (at 200 lfm) four r ja tbd c/w 1,2 junction to case (top) n/a r jc tbd c/w 3 20% tkc v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 1.0 v 50% v dd v il
rev: 1.00e 6/2002 18/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 ac test load diagram ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddi /2 output reference level v ddq /2 input and output le akage characteristics parameter symbol test co nditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua ? mode and zq, mch, mcl, ep1, ep2 pin input current i inm v dd v in v il 0 v v in v il ?2 ua ?50 ua 50 ua 2 ua ? output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua ? selectable impedance output driv er dc electrical characteristics parameter symbol test co nditions min. max notes low drive output high voltage v ohl i ohl = ?4 ma v ddq ? 0.4 v ?1 low drive output low voltage v oll i oll = 4 ma ? 0.4 v 1 high drive output high voltage v ohh i ohh = ?8 ma v ddq ? 0.4 v ?2 high drive output low voltage v olh i olh = 8 ma ? 0.4 v 2 notes: 1. zq = 1; high impedance output driver setting 2. zq = 0; low impedance output driver setting dq vt = v ddq /2 50 ? zq = high (cmos i/o)
rev: 1.00e 6/2002 19/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 operating currents parameter symbol -333 -300 -250 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x36 i ddp pipeline 345 ma 355 ma 320 ma 330 ma 275 ma 285 ma e1 v il max. tkhkh tkhkh min. all other inputs v il v in v ih x18 i ddp pipeline 245 ma 255 ma 225 ma 235 ma 200 ma 210 ma chip disable current x36 i sb1 pipeline 75 ma 85 ma 70 ma 80 ma 65 ma 75 ma e1 v ih min. or tkhkh tkhkh min. all other inputs v il v in v ih x18 i sb1 pipeline 70 ma 80 ma 65 ma 75 ma 60 ma 70 ma bank deselect current x36 i sb2 pipeline 75 ma 85 ma 70 ma 80 ma 65 ma 75 ma e2 or e3 false tkhkh tkhkh min. all other inputs v il v in v ih x18 i sb2 pipeline 70 ma 80 ma 65 ma 75 ma 60 ma 70 ma cmos deselect current i dd3 45 ma 55 ma 45 ma 55 ma 45 ma 55 ma device deselected all inputs v ss + 0.10 v v in v dd ? 0.10 v
rev: 1.00e 6/2002 20/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 ac electrical characteristics parameter symbol -333 -300 -250 unit notes min max min max min max clock cycle time tkhkh 3.0 ? 3.3 ? 4.0 ? ns ? clock high time tkhkl 1.2 ? 1.3 ? 1.5 ? ns ? clock low time tklkh 1.2 ? 1.3 ? 1.5 ? ns ? clock high to echo clock low-z tkhcx1 0.5 ? 0.5 ? 0.5 ? ns 2 clock high to echo clock high tkhch 0.5 1.5 0.5 1.7 0.5 2.0 ns ? echo clock high time tchcl tkhkl +/- 100 ps tkhkl +/- 120 ps ns 2 clock low to echo clock low tklcl 0.5 1.5 0.5 1.7 0.5 2.0 ns echo clock low time tclch tklkh +/- 100 ps tkhkl +/- 120 ps ns 2 clock high to echo clock high-z tkhcz 0.5 1.5 0.5 1.7 0.5 2.0 ns 1, 2 clock high to output in low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? ns 1 clock high to output valid tkhqv 1.6 1.8 2.1 ns ? clock low to output invalid tklqx 1.6 1.8 2.1 ns ? clock low to output valid tklqv 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output invalid tkhqx 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output in high-z tkhqz 0.5 1.6 0.5 1.8 0.5 2.1 ns 1 echo clock high to output valid tchqv ? 0.2 ? 0.2 ? 0.25 ns 2 echo clock low to output invalid tclqx ?0.2 ? ?0.2 ? ?0.25 ? ns 2 echo clock low to output valid tclqv ? 0.2 ? 0.2 ? 0.25 ns 2 echo clock high to output invalid tchqx -0.2 ? -0.2 ? -0.25 ? ns 2 address valid to clock high tavkh 0.6 ? 0.7 ? 0.8 ? ns ? clock high to address don?t care tkhax 0.4 ? 0.4 ? 0.5 ? ns ? enable valid to clock high tevkh 0.6 ? 0.7 ? 0.8 ? ns ? clock high to enable don?t care tkhex 0.4 ? 0.4 ? 0.5 ? ns ? write valid to clock high twvkh 0.6 ? 0.7 ? 0.8 ? ns ? clock high to write don?t care tkhwx 0.4 ? 0.4 ? 0.5 ? ns ? clock high to byte write don?t care tkhbx 0.4 ? 0.4 ? 0.5 ? ns ? data in valid to clock high tdvkh 0.32 ? 0.35 ? 0.40 ? ns ? clock high to data in don?t care tkhdx 0.27 ? 0.30 ? 0.35 ? ns ? notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1.
rev: 1.00e 6/2002 21/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 data in valid to clock low tdvkl 0.32 ? 0.35 ? 0.40 ? ns clock low to data in don?t care tkldx 0.27 ? 0.30 ? 0.35 ? ns adv valid to clock high tadvvkh 0.6 ? 0.7 ? 0.8 ? ns ? clock high to adv don?t care tkhadvx 0.4 ? 0.4 ? 0.5 ? ns ? parameter symbol -333 -300 -250 unit notes min max min max min max notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1.
rev: 1.00e 6/2002 22/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 timing parameter key?read cycle timing tkhqx tkhqz tkhqx1 tkhqv tavkh tkhax ck a dq (ddr) tkhkh tklkh tkhkl cd e qb1 cq tchqv tclqv tclqx tkhch tkhcx1 tkhcz = cq high z tklqx tclch tchcl tchqx tklqv qb2
rev: 1.00e 6/2002 23/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 timing parameter key?control and data in timing jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149. 1-1990, a serial boundary scan interface standard (commonly referred to as jtag) . the jtag port input interface levels scale with v ddi . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to v ddi . tdo should be left unconnected. tkhnx tnvkh tavkh tkhax ck a ab c e1 , e2, e3, w , b n, adv tkhdx tdvkh da1 da2 tkldx tdvkl ddr write dq (data in) note: tnvkh = tevkh, twvkh, tbvkh, etc. and tkhnx = tkhex, tkhwx, tkhbx, etc. db1 db2
rev: 1.00e 6/2002 24/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 jtag port registers overview the various jtag registers, refered to as te st access port or tap registers, are select ed (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers are serial shift registers th at capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructio ns that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in th e scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of th e rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tc k. this is the command input for the tap controller state machine. an undriven tms input w ill produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap cont roller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of t he tap state machine. output changes in response to the falling edge of tck. this is the output si de of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap contro ller is also reset automaticly at power-up.
rev: 1.00e 6/2002 25/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the c ode is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defi ned in the standard 1149.1-1990; standard (public) instructions, and device specific (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads. this device will not perform intest but can perform the prel oad portion of the sample/preload command. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31302928272625242322212019181716151413121110987654321 0 x36 0000000000000001100000011 011001 1 x18 0000000000000001101000011 011001 1 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.00e 6/2002 26/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 when the tap controller is placed in captur e-ir state, the two least si gnificant bits of the instruct ion register are loaded wi th 01. when the controller is moved to the shift- ir state, the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (w hile the previous contents ar e shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register , the bypass register is placed between tdi and tdo. this occu rs when the tap controller is moved to the shift-dr state. this allo ws the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instru c- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bo undary scan register. some boundary scan register locations are not associat ed with an input or i/o pin, and are loaded with the default st ate identified in the bsdl file. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to captur e the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metas table inputs will not harm the device, repeatable results cannot be expected. ra m input signals must be stabilized for long enough to meet the ta p?s input data capture set-up plus hold time (tts plus tth ). the ra m?s clock inputs need not be paused for any other tap operation excep t capturing select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1
rev: 1.00e 6/2002 27/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan re gister between the tdi and tdo pins. the update-dr c ontroller state transfers the contents of boundary scan cells into the holding reg ister of each cell associated with an output pin on the ram. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruct ion register is loaded with al l logic 0s. the extest command does not block or override the ra m?s input pins (except ck); therefore, the ram?s internal state is still determ ined by its input pins. typically, the boundary scan register is loaded with the desired pa ttern of data with the sample/preload command. then the exte st command is used to output the boundary scan register?s contents, in parallel, on the ram?s dat a output drivers on the falling e dge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is sele cted, the state of all the ram?s input and i/o pins, as well as the def ault values at scan register lo cations not associated with a p in, are sampled and transferred in parallel into the boundary scan register on t he rising edge of tck in the capt ure-dr state. boundary scan re gister con- tents may then be shifted serially through the register using the shift-dr command or the controller can be skipped to the upda te-dr com- mand. when the controller is placed in the update-dr state, a ra m that has a fully compliant extest function drives out the val ue of the boundary scan register location asso ciated with which each output pin. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in sh ift-dr mode. the idcode instruction is t he default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z/preload the sample-z instruction operates exactly like sample/preload ex cept that loading the sample-z instruction forces all the ram?s output drivers, except tdo, to an inactive drive state (high-z). rfu these instructions are reserved for future use.
rev: 1.00e 6/2002 28/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z/ preload 010 captures i/o ring contents. places the bounda ry scan register between tdi and tdo. forces all data and clock output drivers to high-z. 1 private 011 private instruction. 1 sample/ preload 100 captures i/o ring contents. places the boun dary scan register between tdi and tdo. 1 private 101 private instruction. 1 private 110 private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v iht 0.65 * v dd v dd +0.3 v1 test port input low voltage v ilt ?0.3 0.35 * v dd v1 tms, tck and tdi input leakage current i inth ?2 2 ua 2 tms, tck and tdi input leakage current i intl ?50 2 ua 3 tdo output leakage current i olt ?2 2 ua 4 test port output high voltage v oht v dd ? 100 mv ?v5, 6 test port output low voltage v olt ? 100 mv v 7 notes: 1. input under/overshoot voltage must be ?1 v < vi < v dd + 1 v with a pulse widt h not to exceed 20% ttkc. 2. v ddi v in v il 3. 0 v v in v il 4. output disable, v out = 0 to v ddi 5. the tdo output driver is served by the v ddq supply. 6. i oh = ?100 ua 7. i ol = +100 ua
rev: 1.00e 6/2002 29/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v ddi ? 200 mv input low level 200 mv input slew rate 1 v/ns input reference level v ddi /2 output reference level v ddq /2 dq v t = v ddq /2 50 ? jtag port ac test load ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.00e 6/2002 30/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 209 bga package drawing 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min typ max units a 1.70 mm a1 0.40 0.50 0.60 mm ? b 0.50 0.60 0.70 mm c 0.31 0.36 0.38 mm d 21.9 22.0 22.1 mm d1 18.0 (bsc) mm e 13.9 14.0 14.1 mm e1 10.0 (bsc) mm e 1.00 (bsc) mm aaa 0.15 mm rev 1.0 a a1 c ? b e e e e1 d1 d aaa bottom view side view
rev: 1.00e 6/2002 31/31 ? 2002, gsi technology, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi rep resentative. preliminary gs8170dd18/36c-333/300/250 ordering information?gsi sigmaram org part number 1 type package speed (mhz) t a 3 512k x 36 gs8170dd36c-333 1x2lp ddr ram 1 mm pitch, 209-pin bga 333 c 512k x 36 gs8170dd36c-300 1x2lp ddr ram 1 mm pitch, 209-pin bga 300 c 512k x 36 gs8170dd36c-250 1x2lp ddr ram 1 mm pitch, 209-pin bga 250 c 512k x 36 gs8170dd36c-333i 1x2lp ddr ram 1 mm pitch, 209-pin bga 333 i 512k x 36 gs8170dd36c-300i 1x2lp ddr ram 1 mm pitch, 209-pin bga 300 i 512k x 36 gs8170dd36c-250i 1x2lp ddr ram 1 mm pitch, 209-pin bga 250 i 1mx 18 gs8170dd18c-333 1x2lp ddr ram 1 mm pitch, 209-pin bga 333 c 1mx 18 gs8170dd18c-300 1x2lp ddr ram 1 mm pitch, 209-pin bga 300 c 1mx 18 gs8170dd18c-250 1x2lp ddr ram 1 mm pitch, 209-pin bga 250 c 1mx 18 gs8170dd18c-333i 1x2lp ddr ram 1 mm pitch, 209-pin bga 333 i 1mx 18 gs8170dd18c-300i 1x2lp ddr ram 1 mm pitch, 209-pin bga 300 i 1mx 18 gs8170dd18c-250i 1x2lp ddr ram 1 mm pitch, 209-pin bga 250 i notes: 1. customers requiring delivery in tape and reel should add th e character ?t? to the end of the part number. example: gs817x18c-300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.

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